Machine Learning for IC Yield: Models, SHAP Explainability & APC/R2R
From fab data to higher yield—predict, optimize, and control.
About This Course
A 3-day, hands-on program to turn fab/process data into higher wafer yield using leakage-safe ML, explainability (SHAP), and R2R/APC. Build and evaluate predictors, prototype virtual metrology, and leave with an actionable, data-backed yield-improvement plan.
Aim
Enable participants to convert fab data into measurable yield gains using leakage-safe ML, explainability, and R2R/APC.
Workshop Objectives
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Learn IC yield fundamentals and baseline analytics.
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Apply leakage-safe ML for yield prediction.
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Gain hands-on experience in feature engineering and model evaluation.
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Optimize processes using R2R/APC and virtual metrology.
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Interpret yield drivers and develop improvement plans.
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Understand MLOps, real-time monitoring, and deployment in fabs.
Workshop Structure
📅 Day 1 – Foundations: Yield and Process Data Analytics
- IC Yield Basics: Understanding yield types and their impact on production costs
- Process Data Overview: Key data sources (MES, SPC, wafer maps) and challenges in data quality
- Baseline Analytics for Yield: Using classical defect models and loss analysis tools
- Hands-on: Explore dataset creation, basic analysis, and yield estimation
📅 Day 2 – Machine Learning for Yield Prediction
- Feature Engineering & Data Preparation: Handling data imbalances and defining features
- ML Models for Yield Prediction: Regression and classification techniques for predicting yield
- Model Evaluation & Interpretability: Key metrics and explainability tools like SHAP
- Hands-on: Build a yield prediction model and interpret results
📅 Day 3 – Optimization and Real-time Control
- Run-to-Run (R2R) Control & APC: Optimizing production parameters with machine learning
- Process Parameter Optimization: Using Bayesian optimization for yield improvement
- MLOps & Digital Twins: Deployment in real-time environments for continuous monitoring
- Hands-on: Apply R2R control, simulate optimization, and present yield improvement strategies
Who Should Enrol?
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PhD scholars & PG students in microelectronics/VLSI/materials/data science
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Academicians & researchers in semiconductor manufacturing or ML
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Fab professionals: process/yield/device/test/metrology/equipment engineers, DFM/PDK, MES/IT, quality/OEE
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Data scientists/ML engineers supporting fab analytics, VM, or APC/R2R
Important Dates
Registration Ends
11/03/2025
IST 4:30 PM
Workshop Dates
11/03/2025 – 11/05/2025
IST 5:30 PM
Workshop Outcomes
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Build and evaluate ML models for yield prediction.
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Apply SPC, Pareto, and classical models for yield analysis.
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Optimize processes using R2R/APC and virtual metrology.
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Implement feature engineering and time-series models.
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Interpret yield drivers using SHAP and permutation importance.
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Develop actionable yield-improvement plans.
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Gain insights into MLOps and best practices for fab data.
Fee Structure
Student
₹1999 | $60
Ph.D. Scholar / Researcher
₹2999 | $70
Academician / Faculty
₹3999 | $80
Industry Professional
₹5999 | $100
What You’ll Gain
- Live & recorded sessions
- e-Certificate upon completion
- Post-workshop query support
- Hands-on learning experience
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